Generally, memory cells of widely used DRAM (dynamic random access memory) devices consist of a capacitor and a transistor. Of such DRAM memory cells, the process for forming a memory cell using a stacked type capacitor will be described as an example.
First, as illustrated in FIG. 1A, oxide layer 2 and nitride layer 3 are successively formed upon semiconductor substrate 1. Then, photo resist is coated on the surface, and a photo-masking process is carried out to form active region pattern 4. Then, as illustrated in FIG. 1B, in order to form an isolating layer, nitride layer 3 and oxide layer 2 are etched by using active region pattern 4 of the photo resist as a mask. The photo resist is removed and field ion implantation 5 is performed. As illustrated in FIG. 1C, an oxidation process is carried out to form isolating layer 6. Then, nitride layer 3 and oxide layer 2 are removed, and an ion implantation is performed for adjusting the threshold voltage.
After completion of this process, as illustrated in FIG. 1D, gate insulating layer 7 is formed on the surface, and polysilicon layer 8 and inter-layer insulating layer 9 composed of silicon oxide are successively deposited for a gate electrode. Then photo resist is coated thereupon, and photo resist pattern 10 is formed through a photo masking process for forming the gate of a transistor.
As illustrated in FIG. 1E, inter-layer insulating layer 9, polysilicon layer 8 and gate insulating layer 7 are successively removed by carrying out an anisotropic etching using photo resist pattern 10 as a mask, thereby forming a gate electrode. Then, impurity ions are implanted to form a lightly doped drain (LDD) region, and an oxide layer is deposited and etched back to form side walls 11 on the sides of the gate electrode. Then an ion implantation is carried out to form a highly doped source/drain region.
Then inter-layer insulating layer 12 is formed, and a contact hole is opened in order to form a contact region which is to be contacted with a node electrode of the capacitor. Then polysilicon is deposited for forming a storage electrode of the capacitor, and node electrode 13, which is the storage electrode, is formed by applying a photo etching process. Dielectric film 14 is coated on the surface of the node electrode, and then plate electrode 15 is formed thereupon. After the completion of the above process, BPSG 16 is formed and spread to flatten the surface, and then metallization layer 17 is formed.
In the conventional stacked type semiconductor memory cell as described above, the capacitance of the capacitor is decided by the surface area, which is decided by the thickness and shape of the storage electrode. There is a limit, however, to the increase of the capacitance, and the stacked contour makes it difficult to carry out the flattening process.
In a modified stacked cell structure in which the shape of the capacitor is varied in various contours, an increase in the capacitance can be achieved to some degree. Due to the complicated nature of the structure, however, short circuits can occur between the node electrode and the plate electrode of the capacitor, with the result that the yield is lowered. Further, the process margin is decreased, so that many problems may be encountered during the formation of the semiconductor device.